MIL-STD-1553B DUAL VMEbus AIM-HY TERMINAL BOARD
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- VMEbus INTERFACE
- DIRECT CONNECT TO SINGLE BOARD COMPUTER (SBC) INTERFACE
- IMPLEMENTS MIL-STD-1553B SPECIFICATION
- DUAL BUS-61553 AIM-HY MODULES
- DUAL INDEPENDENT BC, RT AND MT TERMINALS
- 64KX16 SHARED RAM (EACH TERMINAL)
- PROGRAMMABLE ILLEGALIZATION RAM
- PROGRAMMABLE RT ADDRESS REGISTER
- MT POINTER REGISTER
- EXTERNAL INTERRUPT VECTOR REGISTER
- PROGRAMMABLE BC GAP TIMES
- TIME TAG REGISTER
The LVME/1553-2 Dual 1553 Terminal Board provides full, intelligent interfacing between two independent dual redundant MIL-STD-1553B Data Busses and the VMEbus.
A special Direct Interface, allows the 1553 terminals to be connected directly to a CPU bus located on another VMEbus board, therefore bypassing the VMEbus latency.
Software controls the operation of each independent channel of the LVME/1553-2 as either a MIL-STD-1553 Bus Controller (BC), Remote Terminal (RT) or Bus Monitor Terminal (MT).
At the core of the unit are two ILC DDC Corp dual-redundant BUS-61553 Advanced Integrated Mux Hybrids, operating at 16MHz clock rate . The LVME/1553-2 board may be configured with one or two BUS-61553 components, providing and option to interface with up to two independent 1553 buses using a single double Eurocard.
Each 1553 channel contains 8Kx16 or 64Kx16 of on-board protocol SRAM. The shared RAM is fully double buffered, preventing partially updated data from being read by the VMEbus/CPU host or transmitted to the 1553 data bus.
Each mode of operation (BC, RT and MT) implements sophisticated data buffering structures which reduce the real-time software requirements and off-load the host processor.
- Physical Size
6.3 x 9.19 inches (160mm x 234mm standard double height Eurocard form factor).
- System Bus
VMEbus compatible A24, D16, D8EO type slave.
- Front Panel Indicators
POWER, CH1 RESET, CH2 RESET, DBACT
On-board VMEbus Interrupter.
The LVME/1553-2 provides a user-friendly interface between multiple serial MIL-STD-1553 data buses and the VMEbus or local CPU bus. The interface to each 1553 data bus is implemented through the use of a BUS-61554 Advanced Integrated Mux Hybrid (AIM-Hy) component. The board has the option for one or two Aim components, providing the capability of interfacing with up to two independent 1553 data buses.
The software interface of each 1553 channel is completely independent of the other channels. The operating modes of each of the BUS-61554 are controlled through the use of 12 on-board registers. They include the Configuration Registers, Start/Reset Registers,1553 Time Tag Registers, Interrupt Mask Registers, Interrupt Vector Registers, and RT Address Registers. The Start/Reset Register provides reset and BC/MT start signals. The Interrupt Mask Register enables desired interrupts, with the interrupt priority level being software programmable by the user.
The RT Address Register is programmable by the user software. The 1553 Time Tag Register is used to time tag messages in BC, RT and MT modes.
The LVME /1553 8Kx16 (64Kx16 with external RAM option) of static RAM per channel is shared by the host and 1553 bus with memory arbitration handles automatically by the BUS-61554.
The LVME/1553 will withhold the DTACK* signal to the VMEbus while a word is being transferred to or from the simply stretching the handshake cycle, the wait state is transparent to the CPU's software. A maximum wait of 1.8uS can occur.
The LVME/1553 incorporates complete memory management and processor interface logic. The software interface to the host processor is implemented by means of on-board registers plus the 8K to 64K of RAM per channel. An illegalization RAM is also software loadable.
There are two modes of operation. In the first, the board resources are available through the VMEbus interface. A second option, allows the board resources to be incorporated into a SBC memory map, and the board connected to it through a special P3 connector. When utilizing the Direct Connection feature, the VMEbus timing latency is eliminated, and the 1553 will appear as if it resides directly on the CPU internal bus.
The user may choose to operate the LVME/1553 board in VME only mode, Direct Connect only mode and in mixed mode, all under software control.
Interrupts are enabled by programming the interrupt priority level, interrupt vector and interrupt conditions. The interrupt conditions are selected in the interrupt mask registers. The LVME/1553 board generates an interrupt request on the VMEbus and waits for the bus master to initiate and interrupt acknowledge cycle. Upon receiving an interrupt acknowledge, the board will place an interrupt vector on bits 7 to 0 of the data bus and clear the interrupt request. Further interrupts are disabled until the interrupt is cleared either by an interrupt rest or by reading the interrupt status register. The Interrupt Mask Register enables individual interrupts. The host processor may easily determine the cause of he interrupt by using he Interrupt Status Register. The Interrupt Status Register provides the current state of the interrupt conditions. The Interrupt Status Register may be updated in two ways. In the standard interrupt handling mode, a particular bit in the Interrupt Mask Register is enabled. In the standard interrupt handling mode, a particular bit in the Interrupt Status Register will be updated only if the condition exists regardless of the contents of the corresponding Interrupt Mask Register bit. In any case, the respective Interrupt mask Register bit. In any case, the respective Interrupt Mask register bit enables an interrupt for a particular condition.
The LVME 1553 offers the option to illegalize commands in the RT mode. The illegalization architecture allows for any subset of the 4096 possible combinations of broadcast/own address, T/R bit, word count/mode code and subaddress to be illegalized. The LVME/1553-2 illegalization scheme is under software control of the host processor, and is inherently self testable. There are tow illegalzation mechanisms, one for each 1553 port.
The LVME/1553 incorporates two internal read/writable Time Tag register, one for each 1553 port. These registers are host processor read/writable 16-bit counters with a programmable resolution of 2, 4, 8, 16, 32 or 64uSec per LSB. The Time Tag registers may also be incremented under software control for self-test purposes
MT POINTER REGISTER
The LVME/1553 incorporates two 16-bit MT pointer registers, one for each 1553 port. These registers are read only, and their value appears in the designated MT block word location.
RT ADDRESS REGISTERS
The LVME/1553 incorporates two 6 bit RT address registers, one for each 1553 port. Five bits are for address location while bit 6 is used as the parity bit. The registers are read/writable by the host processor.
In the RELEASE-ON-REQUEST mode, the bus is held until another board asserts a bus request.
The SINGLE-CYCLE mode (release when done) releases the bus at the conclusion of a single bus cycle, which may be read-modify-write, as well as a simple read or write cycle.
The LVME/1553-2 board incorporates a VMEbus Slave interface. It is an A24/D16 slave device. An Interrupt Generator module is also incorporated, including a separate Vector ID register for each 1553 port.
MIL-STD-1553 Bus INTERFACE
The LVME/1553-2 board provides a jumper selectable option for either a direct or transformer-coupled interface.
The LITAL LVME/1553 Terminal Board is a high performance member of LITAL's line of VMEbus boards. The LVME/1553-2 resides on a standard double height Eurocard form factor (160mm x 239mm). The LVME/1553-2 board takes full advantage of the VMEbus architecture and can provide a high performance Dual terminal interface for the VMEbus system or a powerful 1553 element when connected through its Direct Connect Interface to VMEbus Single Board computer.