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LVME/1750AP
MIL-STD-1750A SINGLE BOARD COMPUTER


CLICK ON IMAGE ABOVE TO ENLARGE
  • IMPLEMENTS MIL-STD-1750A NOTICE 1 INSTRUCTION SET ARCHITECTURE
  • 20, 30, 40MHZ PACE 1750A, 1750AE MICROPROCESSOR
  • MEMORY MANAGEMENT UNIT (MMU) AND BLOCK PROTECTION UNIT (BPU)
  • EIGHT JEDEC 32-PIN SITES FOR EPROM/EEPROM/RAM
  • UP TO 1M-WORDS OF ON-BOARD DUAL-PORT STATIC RAM
  • ERROR DETECTION AND CORRECTION
  • ON BOARD START-UP ROM/EPROM
  • OPTIONAL SERIAL CONSOLE INTERFACE
  • TWO PROGRAMMABLE RS232/RS422 SERIAL INTERFACES
  • A24/D16 VMEbus MASTER; VMEbus INTERRUPTER AND INTERRUPT HANDLER
  • MULTIPROCESSING VIA MAILBOX INTERRUPTS
  • VMEbus SYSTEM CONTROLLER WITH PRIORITY AND ROUND ROBIN BUS ARBITER
  • OPTIONAL ON-BOARD SOFTWARE MONITOR AND DIAGNOSTICS
  • FULLY COMPATIBLE WITH LITAL PACE 1750A IN-CIRCUIT EMULATOR
  • ADA AND JOVIAL COMPILERS SUPPORT
  • DIRECT REPLACEMENT TO TASCO ELECTRONICS TVME/1750AP

LVME/1750AP SINGLE BOARD COMPUTER

GENERAL OVERVIEW


The LVME/1750AP Single Board Computer (LVME/1750AP SBC) is a high performance VMEbus compatible module which implements the MIL-STD-1750A instruction Set Architecture (ISA).
The LVME/1750AP was designed to function as a stand-alone microcomputer, as a single CPU/controller in VMEbus systems, or as a single CPU element in a multiprocessor VMEbus environment.

At the core of the unit is the Performance Semiconductor Corp. P1750A CPU, operating at 20, 39, 40 MHz clock rate. The P1750A provides powerful machine resources and computational capabilities while able to execute the MIL-STD-1750A computer instruction set. The LVME/1750AP SBC can contain up to 1M words of on-board EPROM/EEPROM and up to 1M words of on-board static RAM with Error Detection and Correction or Parity Generation and Detection.

Utilizing the P1753 Memory Management Unit (MMU) and a System Definition Register (SDR), the LVME/1750AP SBC is capable of accessing up to 8M words of external memory via the VMEbus. Also, tow programmable multi protocol synchronous/ asynchronous serial interfaces are provided. One RS232, the other RS232, or RS485 compatible. LVME/1750AP SBC fully supports VME compatible multi master configurations and system expansion.

SPECIFICATIONS
  • Physical Size

    6.3 x 9.19 inches (160mm x 234mm standard double height Eurocard from factor).

  • CPU

    P1750A, P1750AE CMOS microprocessor.

  • Memory Configuration

    Eight 32 Pin JEDEC sockets which can be populated as follows:

    • One pair as EPROM/EEPROM/DUAL-PORT RAM.
    • Three pairs as DUAL-PORT RAM only.
    • One pair as EDC RAMs.
    • RAM devices can be 32KB, 128KB, 256KB OR 512KB.
    • EPROM/EEPROM devices can be from 32KB up to 1MB.
    • Four 28-Pin slim sockets which can be populated as follows:
    • One pair as PROM/EPROM (up to 32KB).
    • One pair as parity RAMs (256K or 1Mbit)


  • Memory Management

    Implemented with P1753 MMU. The P1753 maps the logical address space to a 20-bit physical address space; protection of the Logical Space is in 4K word Pages.

    Three additional address bits are available through a programmable register. Eight megawords of memory can be addressed off-board.

  • Block Protection

    Implemented with P1753 MMU. P1753 maps the 1M word space to 1K-block pages. Separate protection is available for CPU and DMA operations.

  • Error Detection and Correction or Parity Generation and Detection

    Implemented with P1753 MMU & P1754 PIC and external static RAMs.

  • VMEbus Time-Out

    The LVME/1750AP generates a Bus Error (BERR) when non-existent devices are addressed on the VMEbus.

  • On-board Bus Time Out

    The LVME/1750AP generates a time out when the CPU accesses non-existent devices.

  • Watch-Dog Timer

    Implemented on the P1754 (PIC).

  • External I/O Access

    16 address lines of I/O space, implemented through use of the A16 mode of VMEbus.

  • Serial I/O

    Two multi-protocol serial port employ the Z8530 Serial Communication Controller.

  • System Bus

    VMEbus compatible A24, D16 type master. On-Board system controller. Even and odd byte transfers, utilized by the System Definition Register.

  • Front Panel Indicators

    FAIL, BERR and SCON.

  • Front Panel Controls

    Reset switch

  • Interrupts

    Supports all seven VMEbus interrupts. Extra on-board interrupts are provided.

    On-Board Interrupts to support serial communication, external CPU accesses and memory error detection.

  • Software Monitor

    Optional LBUG/1750AP EPROM resident monitor provides user control of the LVME/1750AP through serial port 1.

  • Diagnostics

    Optional LBUG/1750AP EPROM resident diagnostics check the operating status of the LVME/1750AP .

  • Temperature

    0 degrees Centigrade to 55 degrees centigrade.

  • Humidity

    0 to 90% non-condensing.

FUNCTIONAL DESCRIPTION

CENTRAL PROCESSING UNIT
(Performance Semiconductor P1750A)

FEATURES


  • Implements the MIL-STD-1750A Instruction Set Architecture.

  • Single Chip CMOS 16-bit Processor with 32 and 48-bit Floating Point Arithmetic Unit.

  • Implements MIL-STD-1750A Options

    • Timers A and B
    • Trigger-Go Reset
    • Start-up ROM Interface

  • 64 Kiloword Address Space Expandable to 1 Megaword with optional MMU chip.

  • TTL Compatible Interface.

MEMORY MANAGEMENT UNIT and BLOCK PROTECT UNIT.
(Performance Semiconductor P1753)

FEATURES


  • Memory management Unit Configuration

    • 1M-Word Physical Address Space organized into 64K-Word Pages
    • Access Lock and key of 4K-Word Blocks
    • Write/Execute Protection of 4K-Word Blocks
    • Memory Fault Status Register
    • BPU Protection of 1K-word Blocks (CPU & DMA)

  • Direct Memory Access Support

  • Error Detection and correction and/or Parity Generation and Detection functions.

  • 1750A Diagnostics

  • TTL compatible Interface

PROCESSOR INTERFACE CIRCUIT
(Performance Semiconductor P1754)

FEATURES


  • Complete interface circuit to the 1750A CPU

    • Programmable READY for memory and I/O
    • Programmable System Watch-Dog (1uSec to 1 minute timer)
    • BIT Software automatically tests the P1750A, P1753 and P1754 as well as the board busses
    • 1750A Diagnostics
    • Parity Generation and Detection (in NON-MMU System)


MEMORY CONFIGURATION AND ADDRESSING

The dual-ported master/slave configuration of the LVME/1750AP SBC enables use of distributed processors and global memory. The memory addressing scheme provides the user with a flexible and efficient system.

The LVME/1750AP SBC supports two jumper configurable memory modes of operation:

a. Start-up ROM Option enabled.
b. Start-up ROM Option Disabled

Start-Up ROM Option Enabled

When Start-up ROM Option is enabled (following power-up or execution of Enable Start-up ROM instruction), all instruction fetches and operand reads are form on-board ROM. All operand stores are to the on-board or off-board RAM. The Start-Up ROM address ranges continuos starting from address 0 up to 0FFFFFH, as required by the system application.

The on-board RAM address range is also continuous starting from address 0 to 3FFFFH when memory size is 256K words.

When the Start-up ROM is disabled (following execution of the Disable Start-up ROM instruction), all instruction fetches, as well as operand reads and stores are from/to on-board./off-board RAM.

Start-up ROM Option Disabled

In this mode, the Start-up ROM enable output of the P1753 is not used. The ROM address range starts from 0 up to 07FFFH and the on-board RAM address starts from 8000H when memory size is 256K words.

The on-board dual-port control logic permits access to on-board RAM via the VMEbus from any master. Segments of on-board RAM may be configured as a private resource protected from VMEbus access. The amount of memory allocated as a private resource is equal to the total on-board RAM less the amount allocated for the VMEbus off-board access.

The segment size of the dual-port RAM as viewed by off-board masters, can be set via jumpers to 64K, 128K, 256K OR 512K words, but cannot exceed the maximum installed memory.

Once the off-board segment size is set, it can be configured to reside anywhere in the 8M word VMEbus address space in increments equal to the selected segment size. Addresses above 1M word range are enabled by means of the System Definition Register (SDR). These features allow multiprocessor systems to establish local memory for each processor and share VMEbus memory configurations in which total system memory size (including local on-board memory) can exceed one megaword without addressing conflicts and without violation of the MIL-STD-1750A addressing standard.

VMEbus REQUESTER/ARBITER

Systems, which permit multiple VMEbus masters to share the data transfer bus, must have an orderly method of dealing with concurrent bus requests. The VMEbus standard requires use of modules, which poses bus request and/or bus arbitration capabilities and the designation of a single VMEbus master as the system controller. The LVME/1750AP employs proprietary programmable logic to implement bus requester and arbiter functions that comply with all bus arbitration protocols of the VMEbus specification. Additional logic provides support of the VMEbus timing and drive requirements.

The LVME/1750 AP may be configured as a system controller to provide the following system management and control functions:

  • VMEbus Arbitration - The system controller accepts bus requests from bus masters on four bus request priority levels, and issues a bus grant to the highest priority requester.
  • System Clock - A 16Mhz-clock signal is provided to other VMEbus devices for counting and synchronizing tasks.
  • Reset - Upon reset, the LVME/1750AP SBC will drive the reset line of the VMEbus if the LVME/1750AP SBC is acting as the system controller.
  • Bus Time-out - The LVME/1750AP SBC will generate a Bus Error (BERR) when a non-existent device is addressed on the VMEbus.

Bus Request Level

When the LVME/1750AP SBC attempts to access an off-board VME bus module, the on-board Bus Controller logic provides a VMEbus request, arbitration and Data Transfer Bus (DTB) cycle to obtain or relinquish VMEbus mastership. Jumpers are provided to select one of the four VMEbus request levels to be used for arbitration.

Bus Arbitration Modes

Two bus arbitration modes are available; each differing in their willingness to relinquish bus mastership once it has been acquired.

In the RELEASE-ON-REAUEST mode, the bus is held until another board assets a bus request.

VMEbus INTERFACE

VMEbus is characterized by the asynchronous bi-directional operation required for complex high performance systems. The VMEbus interface on the LVME/1750AP SBC supports operation in a multiprocessing system and the full 16 megabytes address range. Access to the backplane address, data and control lines is provided by the triple row, 96-pin VMEbus connector. Pin assignments, connector physical characteristics and VMEbus signal and timing requirements are fully described in the VMEbus specification.

The on-board logic, independent of the CPU, generates the signal handshaking and timing required by the VMEbus data transfer protocol.

Bus Timer

The bus timing of the LVME/1750AP SBC incorporates a mechanism for recovering from errors. It does so by reinitializing the time rate the beginning of each new memory or I/O cycle then terminating a data transfer cycle if a response is not received from a slave within a pre-selected period of time. The logic also monitors the local READY*, DTACK* and BERR* and halts the timer when any one of them is asserted in a normal data transfer sequence. If a time-out occurs before any one of them is asserted, RDY* is asserted to the CPU and an interrupt occurs.

Operating Mode Control

The LVME/1750AP SBC provides jumper selectable connections between the arbiter of the VMEbus system control signals and the VMEbus system controller or standard non-controller. Included are the output signal SYSCLK, the bi-directional signal SYSFAIL* and the RESET* input and output signals. When the LVME/1750AP is operated in the isolated mode, none of these signals are connected.

Reset Function

Either the power-on reset logic or the manual reset switch can perform system and local reset.

Serial I/O

The on-board two channel serial communication interface employs the Zilog Z8530 Multi-Protocol Serial Communication Controller (SCC). Two independent software selectable baud rate generators provide the SCC with all common communication frequency. Communication protocols (asynchronous, IBM bisync, or SDLC/HDLC), data formats, control character formats, parity and baud rates are all programmable. Software interface with the SCC can employ either polled or interrupt driven routines. Hardware option allows one channel to be configured as an RS232C, RS422 or RS485 interface whereas the second is RS232C only. The data, command and signal ground lines for each channel are made available via two standard headers.

INTERRUPT HANDLING

The LVME/1750AP SBC supports three classes of interrupts:

a. Local
b. Mailbox
c. VMEbus

Local Interrupts

Local interrupts are those generated by on-board sources. Some local interrupts connect directly to the IOL1 interrupt line of the LVME/1750AP CPU whereas the reminder connect to the fault logic that sets the Fault Register and generates a machine error interrupt. A description of each type of local interrupt is as follows:

SCCINT - Serial Communication Interrupt

There are three types of SCCINT interrupts: Transmit, Receive and External/Status. Each type is enabled under program control with Channel A having higher priority than Channel B, and with Receive, Transmit and External./Status interrupts, prioritize in that order, within each channel. When the Transmit Interrupt is enabled, the CPU is interrupted whenever the transmit buffer have a data character written to into it beforehand so that it is able to become empty. When enabled, the receiver can interrupt the CPU in one of three ways:

  • Interrupt of first Character of Special Condition or Special Receive Condition .
  • Interrupt on All Receive Characters of Special Receive Condition.
  • Interrupt on Special Condition Only.

Interrupt on First Character or Special Condition and Interrupt on Special Condition Only are generally used with the Block transfer mode. A Special Receive Condition is defined as one of the following; receiver overrun, framing error is Asynchronous mode, end-of-frame in SDLC mode and, optionally a parity error. The Special Receive Condition Interrupt differs from an ordinary Receive Character Available interrupts only in the Status that is placed in the vector during and Interrupt Acknowledge cycle. In Interrupt on First Receive Character, and interrupt can occur from Special Receive Conditions any time after the first receive character interrupt.

The main function of the External/Status interrupt is to monitor the signal transitions of the CTS, DCD and SYNC pins. However, an External/Status interrupt can also be initialized by: a Transmit Underrun condition, a zero count in the baud rate generator, by the detection of a Break (Asynchronous mode), Abort (SDLC mode) or EOP (SDLC loop mode) sequence in the data stream. The interrupt caused by the Abort or EOP has a special feature allowing the SCC to interrupt even when an Abort or EOP sequence is detected and terminated. This feature facilitates proper termination of the current message, correct initialization of the next message, and the accurate timing of the Abort condition in external logic while in SDLC mode. In SDLC Loop mode, this feature allows secondary stations to recognize the need of the primary station to retain control of the loop during a poll sequence.

MEM PRT ER* - Memory Protect Error

This interrupt is used to inform the LVME/1750AP CPU of access faults, and execute or write protect violation. Bit 0 of the module Fault Register (FT) is set if this signal goes low during a memory cycle; bit 1 is set if it goes low during a DMA cycle. Either condition immediately sets pending interrupt level 1 and in the case of a memory cycle error, causes the currently executing MIL-STD-1750 A instruction to be aborted.

MEM PAR ER* - Memory Parity Error

Used to inform the LVME/1750AP that a parity error has been detected during memory transfer. Bit 2 of the LVME/1750A Fault Register (FT) is set and causes pending interrupt level 1 to be set.

EX ADR ER* - External Address Error

This signal informs the LVME/1750AP of the occurrence of a Bus Time-Out.

Bit * of the module Fault Register (FT) is set if this signal goes low during a memory fault; bit 5 is set if it goes low during a I/O fault. As with the MEM PRT ER*, either condition immediately set pending interrupt level 1 and causes the currently executing MIL-STD-1750A instruction to be aborted.

SYSTEM WD - System Fault

This interrupt informs the LVME/1750AP CPU that a time-out of the Trigger GO software watchdog timer has occurred. Bits 13 and 15 of the Fault Register (FT) are set.

Mailbox Interrupt

This Mailbox Interrupt is generated any time a write is performed by an off-board CPU within the last 256 words of the on-board selected RAM segment.

This interrupt provides a means for a master CPU to notify the LVME/1750AP SBC of the intent to establish a communication sequence. In systems with more than one master (or intelligent slaves), the Mailbox Interrupt also provides a unique interrupt method to each master outside of the normal seven VMEbus interrupt lines. Moreover, it enables a master to interrupt another master without the need for a conventional VMEbus interrupt. The Mailbox Interrupt is ORed with he SCCINT interrupt and connected to IOL1 int line. Software can recognize the specific interrupt by reading the IOIC1 register.

VMEbus Interrupts

ACFAIL* - Power Down Interrupt

This sets pending interrupt 0 This is the highest priority interrupt and cannot be masked or disabled. (jumper selectable).

SYSFAIL* - VMEbus System Failure

This Signal is asserted whenever the VMEbus SYSFAIL* is active. Bit 7 of the Fault Register is set. (jumper selectable and Software Controlled)

IRQ1* - IRQ7* - VMEbus Interrupt Request 1 to 7

The LVME/1750AP SBC interrupt handler is configured to prioritize VMEbus interrupt requests on any or all seven priority levels.

When more than a LVME/1750AP SBC is utilized on the VMEbus in a multiprocessing environment, each LVME/1750AP is configured to handle a particular subset of the VMEbus interrupt lines. Vectors for IRQ1* through IRQ7* are read from the DTB during an interrupt acknowledge. After gaining bus mastership, the LVME/1750AP SBC places on the lower three address lines the interrupt level to be acknowledged and activates IACK ( along with the appropriate strobe signals. The interrupting device then places the interrupt vector on the lower data byte lines and acknowledge the data transfer.

IRQ1* through IRQ7* are connected to the LVME/1750A interrupts.

WATCH-DOG TIMER

The LVME/1750AP utilizes the Trigger-Go-Reset to implement a WatchDog timer that interrupts the CPU whenever it fails to be reset by software. The timer itself is implemented on the P1754 (PIC) and enables WatchDog timer periods form 1uSec up to 1 minute.

SYSTEM DEFINITION REGISTER (SDR)

The LVME/1750AP SDR is a 16-bit register, which resides in the local I/O space of the CPU and is addressed with an XIO write command to the I/O address 0410H. The function of each bit is as follows:

  • SDR0-SDR2: During VMEbus memory access, these three bits define the values of VMEbus address lines A23, A22, and A21 respectively.

  • SDR3: Enable VMEbus DSO

  • SDR4: Enable VMEbus DS1

  • SDR5: During VMEbus memory access, this bit defines the value of VMEbus address line A20

  • SDR6: Not used

  • SDR7: Enable SYSFLT0 (To accept SYSFAIL*)

  • SDR8: Enable VMEbus Lock

  • SDR9: Turns on the SYSFAIL indicator

  • SDR10: Disables CPU internal time-out

  • SDR11: States VME address modifier code
    '1' = Supervisor
    '0' = Non-Privilege

  • SDR12: Disables VMEbus time-out

  • SDR13 -SDR15: Select VME Bus time-out value.

SYSTEM CONFIGURATION REGISTER (SCR)

The System Configuration Register (SCR) can be read during initialization to establish system configuration. The function of each bit is as follows:

BIT0: '1' = MMU present

BIT1: '1' = BPU present

BIT2: '1' = Console present

BIT3: Coprocessor present

BIT4: interrupt mode: selects the interrupt mode for the Power down and User interrupts. ('1' = level sensitive, "0" = edge sensitive)

BIT5 - BIT15: Reserved.

The SCR is a read-only register, which is automatically updated by an I/O read cycle at address 8410H after Reset or upon execution of the breakpoint instruction (BPT).

LED DISPLAY AND RESET SWITCH

Three LEDs are positioned at the front edge of the LVME/1750AP board to provide a visual indication of its status. One indicates whether the system controller is enabled the second provides an indication of a BERR while the third provides indication of a failure. In addition, a push button switch provides manual system reset capability.

VMEbus CONNECTOR P1

The electrical and mechanical characteristics of VMEbus P1 are fully described in the VMEbus specification document.

The P1 connector provides all signals required to integrate the LVME/1750AP SBC into a VME environment. The basic components of the VMEbus are a 16-bit data bus, a 23-bit address bus, 37 signal lines and the power and ground lines. The SBC is designed to handle all prioritized interrupt levels.

SYSTEM DEVELOPMENT SUPPORT

LITAL provides development support tools for the LVME/1750 AP SBC as follows:

  • P1750A In-Circuit Emulator
  • LBUG/1750AP Monitor
  • LVME/1750 Logic Analyzer pre Processor
  • Serial Console Interface

ADA compilers, Jovial compilers and assemblers that generate MIL-STD-1750A object doe are available from third party sources and are generally hosted on minicomputers or workstations. MIL-STD-1750A code generated by these compilers can easily be downloaded into the LVME/1750AP board memory and debugged using one of the available development tools described below.

In-Circuit Emulator

The LITAL model P1750A In-Circuit Emulator provides the necessary link between the Hewlett-Packard HP64000 development station and the "target" LVME/1750AP SBC. A combination of existing Hewlett-Packard analysis products and the LITAL P1750A ICE yields a powerful set of development and debug capabilities.

The HP 64857A 1750 Assembler/Linker offers full product support for P1750A assembly level code generation. The Assembler generates MIL-STD-1750A object code for either MIL-STD-1750 mnemonics the IEEE/GD mnemonics. Relocatable object modules are passed to the Linker to create an executable absolute file. The Linker also maintains a symbol table with cross-reference information for debugging convenience.

Additional software development tools are available on a variety of computers and can be used to write code for P1750A microprocessors. Also, using the terminal mode, files can be downloaded to take advantage of the highly optimized debugging tools of the HP64000 Development System.

Some of the key features of the LITAL P1750A In-Circuit Emulator include:

  • Register display and modify
  • Memory display and modify
  • Timer display and modify
  • I/O display and modify
  • Run form desired addresses
  • Run until a bread condition
  • Single -Stepping

LBUG/1750AP Monitor

The LITAL LBUG/1750AP Debug Monitor package provides the necessary hardware, software EPROMs and documentation required to interface, through a serial connection, the LVME/1750AP SBC to any software development system for execution and interactive debugging of application software on the target system.

This monitor provides the ability to: Load programs into the target system, execute the programs instruction by instruction or at full speed, set breakpoints and examine/modify CPU registers, memory content and other crucial environment details.

The LVME/1750AP SBC Monitor can be controlled either by a stand-alone terminal or by an external host computer.




LVME/1750AP

LVME/1750AP
The LITAL LVME/1750AP Single Board Computer is a high performance member of LITAL's line of MIL-STD-1750A Single Board Computers. The LVME/1750AP board takes full advantage of the VMEbus architecture and can provide a high performance single CPU system or a powerful element in highly integrated multi-processing applications.

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